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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 15:43:10
-- Design Name: 
-- Module Name: CNT4 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CNT4 is
    Port ( clk : in STD_LOGIC;
           P : inout STD_LOGIC_VECTOR(3 DOWNTO 0));
end CNT4;

ARCHITECTURE ART OF CNT4 IS
  BEGIN
  PROCESS(CLK) IS
    BEGIN
    IF CLK='1'AND CLK'EVENT THEN
      P <=  std_logic_vector((unsigned(P)+1));
    END IF;
  END PROCESS;
END ARCHITECTURE ART;
